1. Field of the Invention
The present invention relates to hardened chip package technology and more particularly to hardened chip package technology against high energy radiation.
2. Description of Related Art
All references listed in the appended list of references are hereby incorporated by reference, however, as to each of the above, to the extent that such information or statements incorporated by reference might be considered inconsistent with the patenting of this/these invention(s) such statements are expressly not to be considered as made by the applicant(s). The reference numbers in brackets below in the specification refer to the appended list of references.
High energy radiation is ubiquitous in the space environment and can cause calculation and memory failures in microelectronic devices (FIG. 1) [Ref. 1]. In addition, with the increase in the integration and density of microelectronic circuit chips, the transistors, which are getting much smaller, are more vulnerable to catastrophic failure mechanisms that can be triggered when high energy radiation or high energy particles, such as heavy ions, protons, alpha particles, and neutrons pass through the device structure.
The present invention provides radiation hardened chip packaging technology that protects avionic devices against high energy radiation during space exploration and high altitude flight. There have been several attempts to reduce radiation damage, such as a new logical design to correct the soft error and a physical design to increase gate charge [Refs. 2 and 3]. However, these methods require an additional volume increase of the microelectronic chip and a resulting higher power consumption, which limits the size and capability of the device. Thus, the implementation of specialized microchips used in aerospace has been slow due to the longer times, higher costs, and limited markets required for separate design and manufacturing of the current style of radiation hardened chips. Unfortunately, even these new configurations cannot promise reliable protection against radiation damage. Other methods are utilizing radiation shielding materials as packaging materials [Refs. 4 and 5]. However, these methods cannot protect against various radiation sources. In addition, the complicated process hinders the use of those technologies in semiconductor chip manufacturing without further investment in facilities.
It is a primary object of the present invention to provide an efficient shielding packaging composed of a multi-layered structure of rare earth element/polymer composites, which can be applicable to any structure of microelectronic circuit chip to protect from a variety of radiation sources from alpha particles and neutrons to high energy electromagnetic radiation.
It is an object of the invention to provide radiation hardened chip packaging technology which can be applicable to current semiconductor chip packaging processes.
It is an object of the invention to provide sensor and actuator devices fabricated with radiation hardened packaging materials.
It is an object of the invention to provide microprocessor and memory chips fabricated with radiation hardened packaging materials.
It is an object of the invention to provide electronic and optoelectronic parts fabricated with radiation hardened packaging materials.
It is an object of the invention to provide electronic and electrical systems protected by radiation hardened packaging technology.
Finally, it is an object of the present invention to accomplish the foregoing objectives in a simple and cost effective manner.
The above and further objects, details and advantages of the invention will become apparent from the following detailed description, when read in conjunction with the accompanying drawings.